1. Field of the Invention
The present invention relates generally to the field of semiconductor packaging. More particularly, the present invention relates to a method for fabricating a wafer level package (WLP).
2. Description of the Prior Art
The semiconductor technologies are developing very fast, and especially semiconductor dies have a tendency toward miniaturization. However, the requirements for the functions of the semiconductor dies have an opposite tendency to variety. Namely, the semiconductor dies must have more I/O pads into a smaller area, so the density of the pins is raised quickly. It causes the packaging for the semiconductor dies to become more difficult.
As known in the art, wafer level package (WLP) packages the dies on a wafer before dividing the dies into respective dies. The WLP technology has some advantages, such as a shorter producing cycle time and lower cost. Fan-out wafer-level packaging (FOWLP) is a packaging process in which contacts of a semiconductor die are redistributed over a larger area through a redistribution layer (RDL) that is typically formed on a substrate such as a TSV interposer.
The RDL is typically defined by the addition of metal and dielectric layers onto the surface of the wafer to re-route the I/O layout into a looser pitch footprint. Such redistribution requires thin film polymers such as BCB, PI or other organic polymers and metallization such as Al or Cu to reroute the peripheral pads to an area array configuration.
In conventional wafer level package processes, two or three temporary carrier bonding processes for wafer handling are required. The carrier provides adequate mechanical support for the molded wafer when handling the wafer.